The system is compromised. Your mission is to analyze the faulty Verilog code, locate the logic errors, and restore functional integrity. Precision and speed are your only allies.
The primary metric. Does the debugged circuit produce the expected functional output for all test cases?
In the event of a tie in accuracy, the team that restores functionality fastest takes the lead.
Judges will evaluate your grasp of the underlying design logic and the elegance of your fix.